8085 MPU (MICRO PROCESSOR UNIT)

(Architecture and Pin Diagram)

8085 is pronounced as "eighty-eighty-five" microprocessor. It is an 8-bit microprocessor designed by Intel in 1977 using NMOS technology [(NMOS is nothing but negative channel metal oxide semiconductor; it is a type of semiconductor that charges negatively. So that transistors are turned ON/OFF by the movement of electrons.)]

It was the first commercially successful microprocessor.

It is used in washing machines, microwave ovens, mobile phones, different electronic devices etc.

 

ARCHITECTURE

8085 consists of the following functional units −

o   Accumulator

It is an 8-bit register used to perform operations like arithmetic, logical, I/O & LOAD/STORE. It is connected to internal data bus & ALU.

 

o   Arithmetic and logic unit

An arithmetic-logic unit (ALU) is the part of a computer processor (CPU) that carries out operations (like addition, subtraction, AND, OR, etc.)  on the operands i.e. 8 bit data in computer system. In some processors, the ALU (arithmetic logic unit) is divided into two units, an arithmetic unit (AU) and a logic unit (LU).

 

o   General purpose register

There are 6 general purpose registers in 8085 processor, i.e. B, C, D, E, H, & L. Each register can hold 8-bit of data.

These registers can work in pair to hold 16-bit data and their pairing combination is like B-C, D-E & H-L.

 

o   Program counter

It is a 16-bit register used to store the memory address location of the next instruction that is to be executed further. Microprocessor increments the program whenever an instruction is being executed, so that the program counter points to the memory address of the next instruction that is going to be evaluated or executed.

 

o   Stack pointer

It is also a 16-bitregister.It works like stack, which is always incremented/decremented by 2 during push & pop operations.

 

o   Temporary register

It is an 8-bit register, which holds the temporary data of arithmetic and logical operations.

 

o   Flag register

It is an 8-bit register having five 1-bit flip-flops, which holds either 0 or 1 depending upon the result stored in the accumulator.

 

 

 

These are the set of 5 flip-flops –

 

·       Sign (S)

·        Zero (Z)

·       Auxiliary Carry (AC)

·       Parity (P)

·       Carry (C)

 

o   Instruction register and decoder

It is an 8-bit register, when an instruction is fetched from the memory then it is stored in Instruction register. Instruction decoder decodes the information present in the Instruction register.

 

o   Timing and control unit

It provides timing and control signal to the microprocessor to perform different operations. Following are the timing and control signals, which control external and internal circuits −

Control Signals: READY, RD’, WR’, ALE

Status Signals: S0, S1, IO/M’

DMA Signals: HOLD, HLDA

RESET Signals: RESET IN, RESET OUT

o   Interrupt control

As the name suggests it controls the interrupts during a process taking place. When a microprocessor is executing the main program and whenever an interrupt occurs, the microprocessor shifts the control from the main program to the incoming request for processing. After the request is completed, the control goes again back to the main program.

 

There are 5 interrupt signals in 8085 microprocessor: INTR, RST 7.5, RST 6.5, RST 5.5,TRAP.

 

o   Serial Input/output control

It controls the serial data communication by using the two instructions:

 SID (Serial input data) and

 SOD (Serial output data).

 

o   Address buffer and address-data buffer

The content stored in the stack pointer and program counter is loaded into the address buffer and address-data buffer to communicate with CPU. The memory and I/O chips are connected to these buses; the CPU can exchange the desired data with the memory and I/O chips.

 

o   Address bus and data bus

Data bus carries the data to be stored. It is bidirectional, whereas address bus carries the location where it should be stored and it is unidirectional. It is used to transfer the data & Address of I/O devices.

 

 

 

8085 ARCHITECTURE (DIAGRAM)

 

 

 

Pin diagram of 8085 microprocessor

 

 

Pin Description The following describes the function of each pin:

·        A6 - A1s (Output 3 State)

Address Bus; The most significant 8 bits of the memory address or the 8 bits of the I/0 address,3 stated during Hold and Halt modes.

·        AD0 - 7 (Input / Output 3state)

Multiplexed Address/Data Bus; Lower 8 bits of the memory address (or I/0 address) appear on the bus during the first clock cycle of a machine state. It then becomes the data bus during the second and third clock cycles. 3 stated during Hold and Halt modes.

·        ALE (Output)

Address Latch Enable: It occurs during the first clock cycle of a machine state and enables the address to get latched into the on chip latch of peripherals. The falling edge of ALE is set to guarantee setup and hold times for the address information. ALE can also be used to strobe the status information. ALE is never 3stated.

·        SO, S1 (Output)

Data Bus Status. Encoded status of the bus cycle:

o   S1 S0

o   0 0 HALT

o   0 1 WRITE

o   1 0 READ

o   1 1 FETCH

 S1 can be used as an advanced R/W status.

·        RD (Output 3state)

READ; indicates the selected memory or 1/0 device is to be read and that the Data Bus is available for the data transfer.

·        WR (Output 3state)

WRITE; indicates the data on the Data Bus is to be written into the selected memory or 1/0 location. Data is set up at the trailing edge of WR. 3stated during Hold and Halt modes.

·        READY (Input)

If Ready is high during a read or write cycle, it indicates that the memory or peripheral is ready to send or receive data. If Ready is low, the CPU will wait for Ready to go high before completing the read or write cycle.

·        HOLD (Input)

HOLD; indicates that another Master is requesting the use of the Address and Data Buses. The CPU, upon receiving the Hold request, will relinquish the use of buses as soon as the completion of the current machine cycle. Internal processing can continue. The processor can regain the buses only after the Hold is removed. When the Hold is acknowledged, the Address, Data, RD, WR, and IO/M lines are 3stated.

·        HLDA (Output)

HOLD ACKNOWLEDGE; indicates that the CPU has received the Hold request and that it will relinquish the buses in the next clock cycle. HLDA goes low after the Hold request is removed. The CPU takes the buses one half clock cycle after HLDA goes low.

·        INTR (Input)

INTERRUPT REQUEST; is used as a general purpose interrupt. It is sampled only during the next to the last clock cycle of the instruction. If it is active, the Program Counter (PC) will be inhibited from incrementing and an INTA will be issued. During this cycle a RESTART or CALL instruction can be inserted to jump to the interrupt service routine. The INTR is enabled and disabled by software. It is disabled by Reset and immediately after an interrupt is accepted.

·        INTA (Output)

 INTERRUPT ACKNOWLEDGE; is used instead of (and has the same timing as) RD during the Instruction cycle after an INTR is accepted. It can be used to activate the 8259 Interrupt chip or some other interrupt port.

o   RST 5.5

o   RST 6.5 - (Inputs)

o   RST 7.5

 RESTART INTERRUPTS; These three inputs have the same timing as I NTR except they cause an internal RESTART to be automatically inserted.

o   RST 7.5 ~~ Highest Priority

o   RST 6.5

o   RST 5.5 o Lowest Priority

 The priority of these interrupts is ordered as shown above. These interrupts have a higher priority than the INTR.

·        TRAP (Input)

Trap interrupt is a non maskable restart interrupt. It is recognized at the same time as INTR. It is unaffected by any mask or Interrupt Enable. It has the highest priority of any interrupt.

·        RESET IN (Input)

Reset sets the Program Counter to zero and resets the Interrupt Enable and HLDA flip flops. None of the other flags or registers (except the instruction register) are affected The CPU is held in the reset condition as long as Reset is applied.

·        RESET OUT (Output)

Indicates CPIJ is being reset. Can be used as a system RESET. The signal is synchronized to the processor clock.

·        X1, X2 (Input)

Crystal or R/C network connections to set the internal clock generator X1 can also be an external clock input instead of a crystal. The input frequency is divided by 2 to give the internal operating frequency.

·        CLK (Output)

Clock Output for use as a system clock when a crystal or R/ C network is used as an input to the CPU. The period of CLK is twice the X1, X2 input period.

·        IO/M (Output)

IO/M indicates whether the Read/Write is to memory or l/O tri stated during Hold and Halt modes.

·        SID (Input)

Serial input data line. The data on this line is loaded into accumulator bit 7 whenever a RIM instruction is executed.

·        SOD (output)

Serial output data line. The output SOD is set or reset as specified by the SIM instruction.

·        Vcc

              +5 volt supply.

·        Vss

               Ground Reference.